1. Field of the Invention
The present invention generally relates to semiconductor memory and, more specifically, to repair and testing of semiconductor memory.
2. Description of Related Art
Semiconductor memory stores data bits organized into rows and columns. Several bits are accessed as a word via functional inputs and outputs. All bits that are accessible via a functional input/output (or I/O) pair is a data bit group.
It is known to provide memory self-repair mechanisms. A typical memory repair method consists of using repair selectors to replace defective data bit groups by defect-free data bit groups. Repair selectors can be implemented as part of the memory (see, for example, Agrawal et al. U.S. Pat. No. 6,507,524 (I/O shifting) and U.S. Pat. No. 6,366,508 (I/O substitution)) or located outside of the memory in a collar so that repair can even be performed on a memory that was not initially designed to support repair. In this case, the designer simply needs to generate a memory with more data bit groups than are needed in functional mode and adding the repair selectors in a collar. This approach is especially useful when the memory is to be made fault-tolerant and repairable in the field because of a latent defect that could not be detected during manufacturing. This fault-tolerance capability requires the capability to change the control signals of the repair selectors after manufacturing.
Many memories with built-in repair support require special equipment, only available at manufacturing time, to permanently program the repair selector control signals. When repair selectors are implemented in a collar external to the memory, the control signals can be re-programmed after manufacturing, but the programming is not permanent. This means that the memory must be tested and the control signals re-programmed each time the circuit containing the semiconductor memory is powered up.
There are two main I/O repair methods. One method is referred to as I/O shifting and the other as I/O substitution. In I/O shifting, the functional input to a defective data bit group is re-directed to the input of the first non-defective neighboring data bit group and the output of the non-defective neighboring data bit group is re-directed to the functional output previously driven by the defective data bit group. The functional input originally connected to the neighboring data bit group is itself re-directed to the input of another non-defective neighboring data bit group and so on. The I/O substitution method redirects the functional input originally connected to a defective data bit group to an identified redundant data bit group. The output of the redundant data bit group is connected to the corresponding functional output. Both methods have advantages and disadvantages that are known to the person skilled in the art.
Both I/O repair methods require running a memory test twice. The first pass is to test the non-redundant data bit groups. Based on the test results, the control signals of the repair selectors are set. Then the memory is tested again to test the repaired memory. There are a number of issues with these methods. First, the two-passes memory test needs leads to longer test times. Second, subtle defects (e.g. bit-line coupling) between data bit groups are not completely covered since only a subset of the data bit groups is exercised during the first and second pass leading to potential quality problems. Third, for applications requiring fault tolerance in the field, the repair logic, including the repair selectors, is not completely tested such that it might not be possible to use a spare data bit group. In addition, when self-repair is implemented, the circuit deriving the control signals of the repair selectors from the test results can be very large.
Huang U.S. Pat. Nos. 6,728,910 and 6,691,264 suggests testing all rows, including redundant rows, of a memory to improve the defect coverage of the memory, but the test and repair still require two passes of the memory test and the coverage of the repair logic is incomplete. Huang is concerned with memories having spare rows and does not address I/O repair methods.
Leader et al. U.S. Pat. No. 6,667,918 suggests a method to repair a memory which is tested by a BIST controller that only provides a binary pass/fail indicator. The repair circuit must then apply several repair configurations and re-test the memory until the binary pass/fail indicates that there are no failures. This method requires extremely long test times.
The foregoing drawbacks are sufficiently significant to justify the development of a new method that would only require a single test pass of the memory test such that test time is reduced. This method should provide a more thorough test of all data bit groups and of their interaction. It should also allow a complete test of the repair logic so that modification of the repair configuration is possible in the field and the circuit deriving the control signals of the repair selectors from the test results should be as small as possible.